Staff Engineer, VLSI Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Job responsibilities:

• Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs
• Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
• Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
• Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, development, debug and closure
• Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities
• Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration
• Create and optimize verification automation tools and scripts to enhance design and verification productivity
• Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration
• Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices

Qualifications

• 8 to 12 years of relevant experience
• Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering

Skills Required/Preferred:

• Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Master's degree preferred
• Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
• Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
• Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
• Proven ability to lead technical projects and manage stakeholder relationships effectively
• Bring in AI/ML/Automation based initiatives
• Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules

Preferred Qualifications:

• Experience with NAND flash memory protocols and memory design verification
• Track record of mentoring junior engineers and contributing to process improvements
• Experience with formal verification methodologies and assertion-based verification

Tools experience/exposure:

• Xcellium simulator, Verdi Debugger, Jaspergold