Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms.
Focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams.
Responsibilities
Execute validation and bring-up activities for DDR and HBM memory subsystems.
Verify memory bring-up software, firmware and scripts against project requirements.
Debug firmware, hardware and system-level issues and contribute to root-cause analysis.
Analyse system logs, validation data and characterization results.
Perform PHY characterization and analog-level analysis during stress testing.
Develop and execute functional, stress, performance and corner-case validation tests.
Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation.
Characterize memory bandwidth, latency, training behaviour and subsystem stability.
Develop Python-based automation, test infrastructure and reporting tools.
Collaborate with architecture, RTL, firmware and platform teams.
Support silicon characterization, production readiness and qualification activities.
Requirements
Strong experience validating DDR, LPDDR, HBM or related DRAM technologies.
Deep understanding of DRAM architecture, memory subsystem operation and memory controller functionality.
Experience with firmware, BIOS and Embedded C development.
Strong programming skills in C and Python.
Hands-on experience with oscilloscopes and measurement instrumentation.
Experience with GPIO, SPI, I2C and UART/serial interfaces.
Experience performing functional testing and signal measurements: voltage, frequency, timing analysis.
Strong knowledge of embedded systems and microcontroller-based platforms.
Hands-on experience with board bring-up and hardware validation.
Desirable: memory IP bring-up environments, DDR/HBM PHY behaviour, training algorithms and calibration flows, memory margining, JTAG, trace infrastructure, signal integrity and power integrity.