About the team
OpenAI's Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design.
About the role
We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.
Responsibilities
- Serve as the physical design SME for semiconductor customer engagements.
- Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans.
- Support customer-facing technical conversations as a trusted advisor.
- Help shape AI-assisted solutions across physical design workflows, including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff.
- Guide feasibility and integration decisions across the entire chip design lifecycle.
- Partner with FDEs and customer SMEs to curate evaluation datasets, golden tasks, rubrics, and acceptance criteria.
- Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools.
- Educate and mentor the broader FDE team on physical design concepts, implementation flows, EDA tooling, and key trade-offs.
- Surface repeated customer signal to Product and Research.
- Progressively take on broader FDE responsibilities.
Requirements
- BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs.
- Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff.
- Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis.
- Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs.
- Strong communication and collaboration skills.
- Strong scripting and automation skills in Python, Tcl, or similar.
- Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role.
Preferred qualifications
- Experience working across multiple semiconductor companies, design environments, or tool stacks.
- Experience partnering with external customers, strategic accounts, or design partners in a technical advisory capacity.
- Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria.
- Exposure to adjacent workflows such as design and/or verification.
- Experience applying AI/LLM systems to semiconductor workflows.
- Prior experience in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical roles.