About the company
Graphcore develops advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design.
Responsibilities
- End-to-end signal integrity analysis for blade- and rack-level system architectures
- Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C
- Perform time-domain and frequency-domain simulations using Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE
- Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes
- Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology
- Collaborate with silicon, package, board, connector, cable, and system design teams
- Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules
- Review schematics, layouts, simulation results, and validation data
- Prepare and communicate validation reports, measurement summaries, debug findings
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Strong experience in signal integrity for high-speed digital systems
- Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes
- Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk
- Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes
- Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, SPICE
- Ability to correlate lab measurements with simulations
- Strong communication skills
Conditions
- Flexible working and comprehensive benefits package
- Medical, dental and vision coverage
- Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs)
- Disability and life insurance, 401(k) retirement plan
- Commuter benefits, wellness services, Employee Assistance Programme (EAP)