Debug Validation Engineer

About the company

• Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
• Develops hardware, software and systems infrastructure for next-generation AI breakthroughs.
• Part of the SoftBank Group.

Responsibilities

• Lead post-silicon debug and validation activities for AI compute silicon and platform technologies.
• Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones.
• Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation.
• Develop structured debug methodologies and failure analysis processes.
• Collaborate with architecture, RTL, firmware, software and systems teams to identify root causes.
• Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions.
• Develop automated debug, regression and validation infrastructure using Python.
• Analyse logs, traces, telemetry and hardware data to isolate system failures.
• Support development of validation tests, debug tooling and custom diagnostics.
• Define validation metrics, debug workflows and reporting standards.
• Support silicon readiness reviews and product quality decisions.

Requirements

• Strong experience in bare metal environments.
• Good knowledge of SoC and platform architectures.
• Expertise in debug infrastructure and post-silicon debug methodologies.
• Strong programming skills in Python, C, or debug scripting languages such as CMM.
• Experience of the post-silicon validation process in digital ASIC environments.
• Strong Linux and Python experience.
• Deep knowledge of scan, DFT, JTAG and trace infrastructure.
• Strong debug skills: fault tree analysis, failure isolation, fishbone methodologies, system-level debug.
• Desirable: understanding of DFT flows, tooling for parsing debug data, driver-level experience with PCIe, Ethernet, LPDDR/DDR/HBM, I2C/I3C/SPI.
• Desirable: CoreSight, CTI, ETx, DStream, JLink, Lauterbach, ATB, STM.
• Desirable: knowledge of PLLs, high-speed PHYs, Arm CPU architectures, AMBA protocols.